Iii-nitride devices including a depleting layer

ABSTRACT

Described herein are lateral III-N (e.g. GaN) devices having a III-N depleting layer, for which the III-N material is formed in an N-polar orientation. The III-N device includes a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N depleting layer. The III-N channel layer includes a 2DEG channel formed therein. The III-N device includes a source electrode and a drain electrode, each of which being electrically connected to the 2DEG channel, and a gate electrode between the source and the drain electrodes, the gate being over the III-N layer structure. The p-type III-N depleting layer includes a first portion that is between the gate and the drain electrode and the p-type III-N depleting layer is electrically connected to the gate electrode and electrically isolated from the source and drain electrodes.

TECHNICAL FIELD

The disclosed technologies relate to semiconductor devices, in particular III-Nitride transistors and switches.

BACKGROUND

Currently, typical power semiconductor devices, including devices such as transistors, diodes, power MOSFETs and insulated gate bipolar transistors (IGBTs), are fabricated with silicon (Si) semiconductor material. More recently, wide-bandgap materials (SiC, III-N, III-O, diamond) have been considered for power devices due to their superior properties. III-Nitride or III-N semiconductor devices, such as gallium nitride (GaN) devices, are now emerging as attractive candidates to carry large currents, support high voltages and provide very low on-resistance and fast switching times. The term device will be used in general for any transistor or switch or diode when there is no need to distinguish between them.

A cross-sectional view of a group-III polar (i.e., Ga-Polar) lateral III-N device 100 is illustrated in FIG. 1 . Devices 100 includes a source contact 21, a drain contact 22, a gate contact 23, and access regions 82 and 83. As used herein, the “access regions” of a device refer to the two regions between the source and gate contacts, and between the gate and drain contacts of the device, i.e., regions 82 and 83 in FIG. 1 . Region 82, the access region on the source side of the gate, is typically referred to as the source-side access region, and region 83, the access region on the drain side of the gate, is typically referred to as the drain-side access region. As used herein, the “gate region” 81 of a device refers to the portion of the transistor between the two access regions 82 and 83 in FIG. 1 . The gate module of the device refers to the portion of the layers and materials of the device that are in or adjacent to the gate region 81 of the device, and within which the electric field is modulated through application of gate voltages in order to modulate the channel conductivity in the gate region of the device. The device channel refers to the conductive region that serves as the current path of the device between the source contact and drain contact when the device is biased in the ON state. The source contact 21 and the drain contact 22 are electrically connected to a lateral two-dimensional electron gas (2DEG) channel 19 (indicated by the dashed line in FIG. 1 ) which is induced in a III-N channel layer 12 adjacent the interface between a III-N barrier layer 13 and the III-N channel layer 12 and serves as the device channel. The III-N material structure of device 100 includes a III-N buffer layer 11 formed over a suitable substrate 10. The III-N channel layer 12 is formed over the III-N buffer layer and the III-N barrier layer 13 is formed over the III-N channel layer 12. The bandgap of the III-N barrier layer 13 is greater than the bandgap of the III-N channel layer 12. The source contact 21, the drain contact 22, and the gate contact 23 are all formed over a side of the III-N material structure opposite the substrate. An insulator layer 18 is formed over the surface of the III-N material structure between the source 21 and the drain 22. If device 100 is a depletion mode device, a portion of the insulator layer 18 can be formed between the gate contact 23 and the top of the III-N material structure, as shown in FIG. 1 . Device 100 includes a field plate 26 which extends over the insulator layer 18 towards the drain 22 in the drain-side access region 83 and is connected to the gate 23. The field plate 26 can help to manage the profile of the electric field in the drain-side access region during operation of the device. However, when the field plate 26 is the primary method used to control the electric field, high electric field peaking can occur at corners of the field plate creating poor electric field uniformity throughout the drain-side access region. As a result, large gate-to-drain spacing is required to fabricate reliable III-N transistors, such as device 100.

Although high voltage Ga-Polar III-N transistors, such as device 100 in FIG. 1 , are beginning to be commercialized, thus far the design and the fabrication of III-N transistors with high figures of merit has proven difficult. Design improvements are needed to improve the size, efficiency and output characteristics of the devices in order to accelerate market adaptation.

SUMMARY

Described herein are lateral III-N (e.g. GaN) devices having a III-N depleting layer (also referred as to a charge compensating layer), for which the III-N material is formed in an N-polar orientation. The device structures can be configured to have stable threshold-voltage, low leakage current, and high breakdown voltages while maintaining a small separation between the gate and the drain ensuring low device on-resistance. The details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.

In a first aspect, a III-N device includes a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N depleting layer. The III-N channel layer includes a 2DEG therein, and the III-N device includes a source electrode and a drain electrode, each of which being electrically connected to the 2DEG channel, and a gate electrode between the source and the drain electrodes, the gate being over the III-N layer structure. The p-type III-N depleting layer includes a first portion that is between the gate and the drain electrode and the p-type III-N depleting layer is electrically connected to the gate electrode and electrically isolated from the source and drain electrodes.

In a second aspect, a transistor includes an N-polar III-N layer structure. The N-polar layer structure includes a III-N channel layer between a III-N barrier layer and a p-type III-N layer. The transistor includes a source electrode, a drain electrode, and a gate electrode between the source and the drain, the gate being over the III-N layer structure and the p-type III-N layer is electrically connected to the gate electrode. The transistor further includes a 2DEG channel in the III-N channel layer, where the N-polar III-N layer structure is configured such that the 2DEG channel extends continuously from the source electrode to the drain electrode when the gate is biased at 0V with respect to the source.

In a third aspect, a transistor includes a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N depleting layer where the III-N channel layer includes a 2DEG channel formed therein. The transistor includes a source electrode and a drain electrode, each of which being electrically connected to the 2DEG channel, and a gate electrode between the source and the drain, the gate being over the III-N layer structure. A first portion of the p-type III-N depleting layer is electrically connected to the gate electrode, and a second portion of the p-type III-N depleting layer is electrically connected to the drain electrode, and the first portion and the second portion are electrically isolated from each other.

In a fourth aspect, a III-N device comprises a III-N layer structure including a III-N channel layer and a 2DEG channel therein, a III-N barrier layer under the III-N channel layer, and a p-type III-N layer over the III-N channel layer. The device further including a source electrode, a drain electrode, and a gate electrode between the source and drain, the gate being over the III-N layer structure and electrically connected to the p-type III-N layer. The p-type III-N layer includes a first portion that is between the gate and the drain electrode. The III-N device has a negative threshold voltage, and the III-N device is configured such that when the gate is biased relative to the source electrode at a negative voltage above a first minimum voltage, the 2DEG channel extends continuously from the source electrode to the drain electrode, and when the gate is biased relative to the source electrode at a voltage below the first minimum voltage and above the threshold voltage, the p-type III-N layer is depleted of holes in the device region between the gate and the drain electrode.

Each of the electronic devices, and transistors described herein can include one or more of the following features. The device can be N-polar device, where the III-N barrier layer is between the III-N channel layer and the III-N buffer layer. The device can have a dopant concentration in the p-type III-N depleting layer such that an areal p-type doping density in the p-type III-N layer is in the range of 10-120% of an areal sheet charge density of mobile charge in the 2DEG channel. The device can have an Al_(x)Ga_(1-x)N layer between the p-type III-N depleting layer and the III-N channel layer, wherein x is between 0.5 and 1, and the thickness of the Al_(x)Ga_(1-x)N layer is between 0.5 nm and 5 nm. The device can have a n-type GaN layer between the gate electrode and the p-type III-N depleting layer. The device can have a second Al_(x)Ga_(1-x)N layer between the n-type GaN layer and the p-type III-N depleting layer, wherein x is between 0.5 and 1, and the thickness of the Al_(x)Ga_(1-x)N layer is between 0.5 nm and 5 nm. The gate electrode can include a field plate, and the field plate can at least partially extend over the first portion of the p-type III-N depleting layer. The drain electrode can include a field plate, and a portion of the field plate can at least partially extend over the first portion of the p-type III-N depleting layer. The device can include a plurality of p-type layers over the III-N channel layer where each layer is separated by an Al_(x)Ga_(1-x)N layer, wherein x is between 0.5 and 1, and the thickness of the Al_(x)Ga_(1-x)N layer is between 0.5 nm and 5 nm. The device can be configured such that, when the gate is biased above the first minimum voltage and the drain electrode is biased above a second minimum voltage, the p-type III-N layer is depleted of holes in the device region between the gate and drain electrode. The first minimum voltage can be below −5V and the second minimum voltage can be above 5V.

As used herein, the terms III-Nitride or III-N materials, layers, devices, etc., refer to a material or device comprised of a compound semiconductor material according to the stoichiometric formula B_(w)Al_(x)In_(y)Ga_(z)N, where w+x+y+z is about 1 with 0≤w≤1, 0≤x≤1, 0≤y≤1, and 0≤z≤1. III-N materials, layers, or devices, can be formed or prepared by either directly growing on a suitable substrate (e.g., by metal organic chemical vapor deposition), or growing on a suitable substrate, detaching from the original substrate, and bonding to other substrates.

As used herein, two or more contacts or other items such as conductive channels or components are said to be “electrically connected” if they are connected by a material which is sufficiently conducting to ensure that the electric potential at each of the contacts or other items is intended to be the same, e.g., is about the same, at all times under any bias conditions.

As used herein, “blocking a voltage” refers to the ability of a transistor, device, or component to prevent significant current, such as current that is greater than 0.001 times the operating current during regular conduction, from flowing through the transistor, device, or component when a voltage is applied across the transistor, device, or component. In other words, while a transistor, device, or component is blocking a voltage that is applied across it, the total current passing through the transistor, device, or component will not be greater than 0.001 times the operating current during regular conduction. Devices with off-state currents which are larger than this value exhibit high loss and low efficiency, and are typically not suitable for many applications, especially power switching applications.

As used herein, a “high-voltage device”, e.g., a high-voltage switching transistor, HEMT, bidirectional switch, or four-quadrant switch (FQS), is an electronic device which is optimized for high-voltage applications. That is, when the device is off, it is capable of blocking high voltages, such as about 300V or higher, about 600V or higher, or about 1200V or higher, and when the device is on, it has a sufficiently low on-resistance (R_(ON)) for the application in which it is used, e.g., it experiences sufficiently low conduction loss when a substantial current passes through the device. A high-voltage device can at least be capable of blocking a voltage equal to the high-voltage supply or the maximum voltage in the circuit for which it is used. A high-voltage device may be capable of blocking 300V, 600V, 1200V, 1700V, 2500V, 3300V or other suitable blocking voltage required by the application. In other words, a high-voltage device can block all voltages between 0V and at least V_(max), where V_(max) is the maximum voltage that can be supplied by the circuit or power supply, and V_(max) can for example be 300V, 600V, 1200V, 1700V, 2500V, 3300V or other suitable blocking voltage required by the application. For a bidirectional or four quadrant switch, the blocked voltage could be of any polarity less a certain maximum when the switch is OFF (±V_(max) such as ±300V or ±600V, 1200V and so on), and the current can be in either direction when the switch is ON.

As used herein, a “III-N device” is a device based on or essentially including III-N materials, including III-N heterostructures. The III-N device can be designed to operate as a transistor or switch in which the state of the device is controlled by a gate terminal or as a two terminal device that blocks current flow in one direction and conducts in another direction without a gate terminal. The III-N device can be a high-voltage device suitable for high voltage applications. In such a high-voltage device, when the device is biased off (e.g., the voltage on the gate relative to the source is less than the device threshold voltage), it is at least capable of supporting all source-drain voltages less than or equal to the high-voltage in the application in which the device is used, which for example may be 100V, 300V, 600V, 1200V, 1700V, 2500V, or higher. When the high voltage device is biased on (e.g., the voltage on the gate relative to the source or associated power terminal is greater than the device threshold voltage), it is able to conduct substantial current with a low on-voltage (i.e., a low voltage between the source and drain terminals or between opposite power terminals). The maximum allowable on-voltage is the maximum on-state voltage that can be sustained in the application in which the device is used.

As used herein, a “III-polar” or “group-III polar” III-N material is a III-N material for which the group-III face (i.e., the [0 0 0 1] face) is opposite the substrate on which the material is grown. In a “III-polar” or “group-III polar” lateral III-N device, at least some of the device contacts (e.g., the source and/or drain contacts) are typically formed on a [0 0 0 1] face of the III-N material (e.g., on a side opposite the [0 0 0-1] face).

As used herein, an “N-polar” III-N material is a III-N material for which the Nitrogen face (i.e., the [0 0 0-1] face) is opposite the substrate on which the material is grown. In an “N-polar” lateral III-N device, at least some of the device contacts (e.g., the source and/or drain contacts) are typically formed on a [0 0 0-1] face of the III-N material (e.g., on a side opposite the [0 0 0 1] face).

As used herein, a “regrown” III-N layer structure or III-N material structure, refers to an additional material deposition process which is performed after previous material deposition processes. Between subsequent growth and regrowth processes, the device can be unloaded from the deposition tool and the vacuum environment can be interrupted. As such, a regrown III-N material structure can require a separate insertion into the III-N material structure deposition equipment from the initial III-N material structure insertion. For example, a regrown III-N layer can be deposited after a removal of at least a portion of an initial III-N material structure. The removal of a portion of the initial III-N material structure typically occurs in an environment outside the primary III-N material structure deposition equipment.

The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one layer with respect to other layers. As such, for example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer “on” a second layer is in contact with that second layer. Additionally, the relative position of one layer with respect to other layers is provided assuming operations are performed relative to a substrate without consideration of the absolute orientation of the substrate.

The details of one or more disclosed implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Additional features and variations may be included in the implementations as well. Other features, aspects, and advantages will become apparent from the description, the drawings and the claims.

DESCRIPTION OF DRAWINGS

FIG. 1 is a cross-section view of a Ga-Polar III-N devices of the prior art.

FIG. 2 is a cross-sectional view of a depletion-mode N-Polar III-N device having a III-N depleting layer.

FIGS. 3A and 3B area detailed cross-sectional views of the III-N material layer structures forming a gate connection.

FIGS. 4A-4F are alternative embodiments of the III-N device of FIG. 2 .

FIGS. 5A-5G are cross-sectional views of N-Polar III-N devices having III-N depleting layers below the III-N channel layer.

FIG. 6 is a cross-sectional view of an enhancement-mode N-Polar III-N device having a III-N depleting layer.

FIG. 7 is a cross-sectional view of a bi-directional III-N device having a III-N depleting layer.

DETAILED DESCRIPTION

Described herein are lateral III-N devices that have a III-N layer which is used as a channel charge depleting layer (also referred as to a charge compensating layer), for which the III-N material structure of the device is grown in an N-Polar (i.e., N-face) orientation, such as the [0 0 0-1] orientation, where the bracket notation indicates the Miller index orientation of the material lattice structure. Specifically, the III-N depleting layer can cause a portion (or the entirety) of the 2DEG channel charge in an access region of the transistor to be partially or fully depleted when the gate of the transistor is biased relative to the source at a voltage lower than a certain value (e.g., −5V, −10V, or −20V), but not to be partially or fully depleted while the transistor is biased ON (e.g., when the gate of the transistor is biased relative to the source at a voltage similar, equal, or higher than 0V). Such a structure allows for a compact transistor with a very high breakdown voltage while maintaining a low on-resistance.

Typical III-N high electron mobility transistors (HEMTs) and related devices, such as device 100 of FIG. 1 , are formed on III-Nitride materials grown in a group-III polar (e.g., Ga-polar) orientation, such as the [0 0 0 1] (C-plane) orientation, as shown in FIG. 1 . That is, the source, gate, and drain contacts of the HEMT are formed over the group-III face (e.g., [0 0 0 1] face) of the III-N material layers, which is typically on an opposite side of the III-N material layers from the substrate on which the III-N layers are formed. Alternatively, III-N HEMTs can be formed on III-Nitride materials grown in an N-Polar (i.e., N-face) orientation, such as the [0 0 0-1] orientation. In this case, the source, gate, and drain contacts of the HEMT are formed over the N-face (e.g., [0 0 0-1] face) of the III-N material layers. N-polar III-N materials have polarization fields with an opposite direction than group-III polar III-N materials, thus can enable the implementation of III-N devices which cannot be fabricated using group-III polar structures. In addition, N-polar III-N devices have demonstrated superior electrical characteristics when compared to similar sized group-III polar devices, including lower static and dynamic on-resistance, with higher current density, and higher power density.

III-N devices with charge depleting layers can be advantageous with N-polar III-N materials with respect to Ga-polar III-N materials for at least the following reasons. First, when used in a N-polar III-N device, a channel depleting layer does not significantly affect the mobility and charge density of the 2DEG channel between the source and drain electrodes compared to a Ga-polar III-N device. Therefore, the 2DEG sheet resistance of an N-polar III-N device can be reduced, even with a channel depleting layer (for example lower than 450 Ω/sq, or lower than 300 Ω/sq) formed above the 2DEG channel, which is required to improve the device on-state resistance. Second, N-polar III-N materials offer additional design possibilities, described in the following figures, to form a channel depleting layer with a high dopant ionization efficiency (for example, the ratio between hole concentration and acceptor concentration in p-type layers is higher than 10% or higher than 50%), high hole mobility (for example higher than 10 cm²/Vs) and low contact resistance (for example, lower than 1 Ωcm² or lower than 10⁻³ Ωcm²) essential for fast transient time (turn-on and turn-off) and small switching losses. Furthermore, N-polar material structures offer the possibility of integrating high-voltage charge-depleting modules with normally-off enhancement-mode gate-modules with a p-type body (as further described in FIG. 6 ).

Referring to FIG. 2 , an N-polar depletion-mode III-N device 200 is shown. The III-N device 200 includes a III-N buffer layer 11, for example GaN or AlGaN, grown on a suitable substrate 10, which can for example be silicon (Si), silicon carbide (SiC), sapphire, AlN, or GaN. The substrate can be electrically conductive (e.g., p-type Si), electrically semi-insulating (e.g., SiC), or electrically insulating (e.g. sapphire). The substrate can be thinned to improve thermal dissipation, for example to a thickness of less than 200 μm. The substrate can have a similar (e.g., within 10%) or different lattice constant and/or thermal expansion coefficient than that of any of the material layers of the III-N structure. When the lattice constant and/or thermal expansion coefficient between the substrate and the III-N layers are different, a nucleation and/or stress-relief management layer can be introduced between the substrate 10 and the buffer layer 11 (not shown). The substrate 10 can be either floating (i.e., no fixed potential) or grounded (i.e., the substrate potential is fixed at the same voltage of the source). In some implementations the substrate 10 may be omitted.

The buffer layer 11 can be rendered insulating or substantially free of unintentional n-type mobile carriers by including dislocations or point defects in the layer, or by doping the layer with compensating elements, such as Fe, C, and/or Mg. The buffer layer can have a substantially uniform composition throughout, or the composition can vary. For example, in some implementations the buffer layer is compositionally graded, such as by grading the aluminum composition along a vertical axis in the buffer layer. The buffer layer 11 can be substantially thicker than any of the other III-Nitride layers in the structure. For example, buffer layer 11 may have a thickness that is at least 5 times, but typically at least 10 times, the combined thickness of the III-N layers between buffer layer 11 and the gate 23. N-polar III-N devices may allow thinner buffer layer 11 than Ga-polar III-N devices due to the growth conditions which can lead to a higher quality nucleation layer and better dislocation management in the buffer layer 11 on foreign substrates.

The III-N device 200 further includes a III-N back-barrier layer 14, for example Al_(x)Ga_(1-x)N, over the III-N buffer layer 11, and a III-N channel layer 15, for example unintentionally doped (UID) GaN, over the III-N back-barrier layer 14. The bandgap of the III-N back-barrier layer 14 is greater than that of the III-N channel layer 15. The III-N channel layer 15 has a different composition than the III-N back-barrier layer 14, and the thickness and composition of each of the III-N back-barrier layer 14 and III-N channel layer 15 is selected such that a conductive layer of electrons is induced in the III-N channel layer 15. The interface between the III-N back-barrier layer 14 and the III-N channel layer 15 can be abrupt. In that case, a conductive two-dimensional electron gas (2DEG) channel 19 (indicated by the dashed line in FIG. 2 ) is induced in the III-N channel layer 15 adjacent the interface between layers 14 and 15. The composition of the III-N back-barrier layer 14 and III-N channel layer 15 can be constant or can be varied throughout. For example, the layer 14 can have a first portion that is a graded AlGaN portion with an increasing Al concentration (for example with the lowest Al concentration on the side nearest the substrate), and a second AlGaN portion that has a constant Al concentration. In another example, the III-N back barrier layer has a first portion that is n-type GaN or AlGaN and a second portion that is undoped AlGaN. The III-N back barrier layer 14 can include a first portion (near the substrate) that is a n-type III-N portion, a second portion over the first portion that is a graded III-N portion (e.g., the aluminum composition is graded) and a third portion over the second portion that has a constant composition. Furthermore, the graded portion or the n-type portion of the III-N back-barrier layer 14 can be doped with Si or any other dopant that prevents the formation of holes. The doping concentration per unit area can be in a range of 1e11 donors/cm² to 1e14 donors/cm². Preferably, the doping concentration is selected such that the equivalent areal density (expressed in cm⁻²) is similar to (e.g., within +50% of) the areal charge density in the 2DEG channel.

The different portions of the III-N back barrier layer 14 can act to prevent the formation of a parasitic two-dimensional hole-gas near the bottom of the back-barrier layer. For example, if holes accumulate near the bottom of the back-barrier, the device may suffer from parasitic leakage current and threshold voltage instabilities due to hole-trapping. If the doping of the layer is too low, parasitic hole accumulation can occur; however if the doping is too high, parasitic electron accumulation can occur near the bottom of the back-barrier layer 14. Mobile carriers (either holes and/or electrons) can be reduced in the back-barrier layer 14 and/or buffer layer 11 by adding impurities (such as carbon, other amphoteric dopants or deep-level traps) that can trap excess mobile carriers and pin (stabilize) the Fermi-level within the band-gap sufficiently distant from both valence-band and conduction-band (e.g., E_(V)+0.5 eV, E_(V)+0.9 eV, E_(C)−0.6 eV, etc.).

The back-barrier layer 14 can have a thickness between 5 nm and 50 nm. The back-barrier layer 14 can have a thickness greater than 15 nm. The channel layer 15 can have a thickness between 2 nm and 300 nm. The channel layer 15 can have a thickness that is greater than 15 nm. The thickness of the channel layer 15 can determine the threshold voltage (V_(TH)) of the device. For example, a channel layer 15 thickness that is lower than 30 nm can result in a threshold voltage higher than −10 V. Minimizing the negative threshold-voltage for a depletion-mode device can be useful when used in cascode configuration with a low-voltage enhancement-mode FET, preventing the enhancement-mode FET from entering avalanche-mode during the off-state, or from being biased outside the Safe-Operating Area, therefore undergoing thermal runaway during short-circuit events. In addition, a 0.5-5 nm Al_(x)Ga_(1-x)N interlayer (where x>50%, not shown) can be disposed between the barrier layer 14 and the channel layer 15. This Al_(x)Ga_(1-x)N interlayer can help to increase the polarization charge and reduce electron scattering at the interface between the III-N back-barrier layer 14 and the III-N channel layer 15, improving the 2DEG channel sheet-resistance. For example, the 2DEG channel sheet-resistance can be between 500 Ω/sq to 150 Ω/sq. Preferably, the 2DEG channel sheet-resistance is lower than 400 Ω/sq.

In another example, a portion of the III-N channel layer 15 can have bulk n-type conductivity generated through either impurity doping (e.g., silicon incorporation) and/or polarization-doping. To achieve polarization-doped n-type conductivity, the composition of the III-N channel layer 15 is graded such that the gradient of the polarization field is negative in the [000-1] direction. For example, the III-N channel layer 15 in the III-N device 200 can be formed of Al_(y)Ga_(1-y)N (0≤y≤1), where at the side adjacent the III-N back-barrier layer 14, y is equal to the y in the III-N back-barrier layer 14, and where y decreases (e.g., continuously decreases) from the side adjacent the III-N back-barrier layer 14 to the side opposite the III-N back-barrier layer 14. Alternatively, the III-N channel layer 15 can be formed of In_(y)Ga_(1-y)N (0≤y≤1), where y increases (e.g., continuously increases) from the side adjacent the III-N back-barrier layer 14 to the side opposite the III-N back-barrier layer 14.

A III-N depleting layer 16 is formed over at least a portion of the III-N channel layer 15. Specifically, the III-N depleting layer can cause a portion (or the entirety) of the 2DEG channel charge in an access region of the transistor to be partially or fully depleted when the gate of the transistor is biased relative to the source at a voltage lower than a certain negative value (e.g., V_(GS)=−5V, −10V, or −20V), but not to be partially or fully depleted while the transistor is biased higher than a certain value (e.g., V_(GS)=−1V, 0V or more than 0V). The III-N depleting layer can act as a charge compensating layer that, when the device is biased OFF, compensates a portion or the entirety of the ionized positive charge in the channel layer 15 and AlGaN back-barrier layer 14 with ionized negatively charged acceptors, and does not affect the 2DEG charge when the device is biased ON.

As shown in FIG. 2 , the III-N depleting layer 16 can be over the channel layer in the gate region 81 and laterally extending into the drain-side access region 83 between a gate contact 23 and the drain contact 22. The III-N depleting layer includes a first end and a second end, the first end being adjacent to the source contact 21 and the second end being adjacent to the drain contact 22. The III-N depleting layer 16 is electrically isolated from the drain contact 22 through a lateral separation 25. The separation from the second end of depleting layer 16 to the drain contact 22 can be between 0.5 μm and 10 μm, preferably less than 5 μm. Optionally, a portion of the III-N depleting layer 16 can also extend into the source-side access region 82. The III-N depleting layer 16 is electrically isolated from the source contact 21 through lateral separation 27. The separation from the first end of depleting layer 16 to the source contact 21 can be between 0.5 μm and 10 μm, preferably less than 5 μm. The lateral separation 25 can be the same or different than the lateral separation 27. For example, the lateral separation 25 can be greater than the lateral separation 27 in order to support higher drain-to-gate voltages (V_(DG)), which may require a larger separation than what is required to support the gate-to-source voltages (V_(GS)). The III-N depleting layer 16 can be formed over the entire III-N channel layer and then removed (e.g., by dry and/or wet etching) in a portion of the source-side access region 82 adjacent the source contact 21 and in a portion of the drain-side access region 83 adjacent to the drain contact 22.

The III-N depleting layer 16 can be realized by a single III-N layer or by multiple III-N layers with varying Al composition. The III-N depleting layer 16 can be p-type. The p-type doping can be provided by impurity incorporation (e.g., magnesium) or by polarization engineering (e.g., positive polarization field gradient in the [000-1] direction). The p-type doping distribution across the depleting layer 16 can have a uniform or a graded profile. The depleting layer 16 can have a box profile or a delta-function profile. The depleting layer 16 can have multiple repetitions of any of the above profiles.

The p-type doped III-N depleting layer 16 can be doped with an active acceptor concentration greater than 1×10¹⁶ cm⁻³ and lower than 2×10²⁰ cm⁻³, for example greater than 1×10¹⁸/cm⁻³. Acceptor concentration can be lower than 3×10¹⁹ cm⁻³ to avoid excessive incorporation of impurities (such as carbon and hydrogen) which can be detrimental for ionization rate and hole mobility. If the III-N depleting layer 16 is p-type doped with Mg, the device can be treated with high temperature annealing to render Mg dopants electrically active. The III-N depleting layer 16 can have a thickness between 1 nm and 1 μm. For example, the III-N depleting layer 16 can have a thickness greater than 4 nm and less than 80 nm.

The depleting layer 16 can be designed such that, when operated in the off-state, the areal density of ionized negative charge in the depleting layer 16 is in the 10%-150% range of the areal density of ionized positive charge in the channel layer 15 and in the AlGaN back-barrier layer 14 (ionized negative and positive charge can account for ionized acceptors, ionized donors, spontaneous and piezoelectric polarization charges, ionized deep-levels, ionized interface states). In some embodiments, the ratio between ionized negative charge and ionized positive charge can be between 90% and 110%. However, due to process variability and difficulty in controlling the doping density of the charge depleting layer 16, it is possible that the ionized negative charge of the depleting layer 16 can be significantly smaller (e.g., less than 70% or less than 40%) or greater (e.g., higher than 120%) than the ionized positive charge in the channel layer 15 and in the AlGaN back-barrier layer 14. The discrepancy between ionized positive charge and negative charge can be factored in the device design. Device embodiments to improve the electric field uniformity in the case of discrepancy between ionized positive and ionized negative charges are described later. The depleting layer 16 can be designed so that it becomes substantially fully ionized (fully depleted) when the gate voltage relative to the source (V_(GS)) is sufficiently negative below a minimum value (for example, −5V, −10V, or −20V) that can be smaller, similar, or greater than the threshold voltage of the device. Additionally, the depleting layer 16 can become partially or substantially fully ionized (depleted) in the drain-side access region 83 when the gate is biased ON (above the threshold voltage of the device, for example at 0V) and the drain voltage exceeds a second minimum voltage (such as 10V, 20V, 30V, 100V, etc.). The depleting layer 16 can become partially or substantially fully ionized (depleted) in the drain-side access region 83 when the device is operated in on-state saturation regime (linear-mode).

When the depleting layer 16 is fully ionized (depleted), it can block high voltages while improving the electric field uniformity in the device. The depleting layer 16 can be designed such that, when operated in the on-state, the ionized acceptors in the depleting layer 16 are neutralized by positive carriers (holes) to allow drain-source current to flow. The depleting layer 16 can be designed such that, during the turn-on and turn-off transitions, the neutralization and the ionization of the depleting layer 16 are sufficiently rapid to ensure sufficiently fast device switching time (e.g., lower than 20 ns) and sufficiently low switching losses. Ionization and neutralization of the depleting layer 16 can be improved by lowering the resistivity of the depleting layer 16 and/or by lowering the contact resistance between the depleting layer 16 and the gate contact 23.

Low resistivity of the depleting layer 16 can be achieved by improving hole-mobility and by increasing the acceptor ionization efficiency (e.g., higher number of holes for the same number of acceptors). For example, ionization efficiency can be higher than 1%, or higher than 10% or higher than 50%, and hole mobility can be higher than 5 cm²/Vs or higher than 10 cm²/Vs. High hole-mobility and/or high acceptor ionization efficiency can be achieved with p-type modulation doping III-N heterostructures, for example, the depleting layer 16 can be formed with an Al_(x)Ga_(1-x)N layer (x can be high enough such that the valence-band discontinuity between III-N depleting layer 16 and the channel layer 15 is larger than the ionization energy of the p-type acceptor). In another example, the depleting layer 16 can be formed with a thin GaN layer (0.5-5 nm) deposited on top of a thin Al_(x)Ga_(1-x)N layer (0.5-5 nm, where x can be higher than 50%, x can be high enough such that the valence-band discontinuity between the thin GaN layer 16 and the thin Al_(x)Ga_(1-x)N layer is larger than the ionization energy of the p-type acceptor). In another example, the depleting layer 16 can be formed with a periodic repetition (superlattice) of thin GaN layers deposited on top of thin Al_(x)Ga_(1-x)N layers (where x can be higher than 50%). The p-type doping distribution in the III-N heterostructure can have a uniform profile, or it can have a box profile, or it can have a delta-function profile. Each III-N layer comprising the p-type modulation doping superlattice can have a thickness between 0.1 nm and 10 nm. Preferably, the Al_(x)Ga_(1-x)N layers in the p-type modulation doping superlattice can have a thickness smaller than 3 nm or smaller than 2 nm. For example, a p-type modulation doping III-N heterostructure can be comprised of a thin Al_(x)Ga_(1-x)N layer, a thin p-type GaN layer and a thin Al_(x)Ga_(1-x)N layer deposited on top of the III-N channel layer 15, where a 2 dimensional hole gas (2DHG) forms at the interface between the III-N channel 15 and the first thin AlGaN layer and the p-type GaN has a high ionization efficiency (higher than 90%).

In addition, a 0.5-5 nm AlGaN or AlN interlayer (shown as layer 34 in FIG. 3A) can be disposed between the III-N depleting layer 16 and the channel layer 15. This AlGaN or AlN interlayer can help prevent undesired Mg diffusion from the Mg-doping of the p-type III-N depleting layer into the III-N channel layer 15. This AlGaN or AlN interlayer can also serve as selective etch stop-layer to improve the control and the accuracy of the etching process used to remove the III-N depleting layer 16 in the drain side and source side access regions.

Alternatively, returning to FIG. 2 , the p-type of the III-N depleting layer 16 can be achieved by polarization-induced doping (e.g., by grading the bandgap of the layer without introducing any dopant impurities). In this case, an aluminum or indium composition of the III-N depleting layer 16 is graded to induce a bulk negative polarization-charge which can attract holes, rendering the III-N depleting layer 16 p-type. A graded III-N depleting layer 16 has a composition that is graded (e.g., continuously graded), from the side adjacent the III-N channel layer 15 to the side opposite the III-N channel layer 15. The composition of a graded p-type III-N depleting layer 16 is selected such that the gradient of the polarization field is positive in the [000-1] direction. For example, the III-N depleting layer 16 in the III-N device 200 can be formed of Al_(y)Ga_(1-y)N (0≤y≤1), where at the side adjacent the III-N channel layer 15 y is equal to the y of the III-N channel layer 15, and where y increases (e.g., continuously increases) from the side adjacent the III-N channel layer 15 to the side opposite the III-N channel layer 15. Alternatively, the III-N depleting layer 16 can be formed of In_(y)Ga_(1-y)N (0≤y≤1), where y decreases (e.g., continuously decreases) from the side adjacent the III-N channel layer 15 to the side opposite the III-N channel layer 15.

The gate contact 23 may be in direct contact with the III-N depleting layer 16. Alternatively, in order to improve the electrical connection between the gate contact 23 and the III-N depleting layer 16, an optional III-N contact layer 17 can be used, for example a n-type GaN layer, which is at least formed over the III-N depleting layer 16 in the gate region 81 of device 200 between the gate 23 and the III-N depleting layer 16. The thickness of the III-N contact layer 17 can be between 10 nm and 1 μm. The III-N contact layer 17 can be doped with donors, for example silicon. The doping concentration of the III-N contact layer can be high enough to yield an electron concentration density greater than 1×10¹⁶ cm⁻³. The thickness and net n-type doping of the III-N contact layer 17 can be sufficiently high such that layer 17 is not fully depleted of free electrons by the III-N depleting layer 16, for example thickness can be greater than 50 nm and average n-type doping greater than 1×10¹⁸ cm⁻³. The n-type doping can be greater than 1×10¹⁹ cm⁻³.

Alternatively, to ease manufacturability, III-N contact layer 17 can be, for example, a p-type GaN layer. The thickness of a p-type III-N contact layer 17 can be between 10 nm and 1 μm. The III-N contact layer 17 can be doped with donors, for example magnesium. The doping concentration of the III-N contact layer can be high enough to yield a hole concentration density greater than 1×10¹⁶ cm⁻³. The thickness and net p-type doping of the III-N contact layer 17 can be sufficiently high such that layer 17 has a higher p-type doping density than that of the III-N depleting layer 16. For example, the thickness of layer 17 can be greater than 50 nm and average p-type doping greater than 1×10¹⁸ cm⁻³. The p-type doping can be greater than 1×10¹⁹ cm⁻³.

The III-N contact layer 17 is removed in a portion of the source side and drain side access regions. The III-N contact layer can be left in place in the gate region 81. The length of the gate region 81 can be between 10 nm and 10 μm, for example between 0.5 μm and 3 μm. The gate aspect-ratio can be defined as the ratio between the length of the gate region 81 and the thickness of the III-N channel 15. The gate aspect ratio can be sufficiently large, for example greater than 5, to prevent Drain-Induced Barrier Lowering (DIBL) parasitic effects under high drain bias conditions. The process of removing the III-N contact layer 17 can be selected to substantially minimize damage to the exposed surface of the III-N depleting layer 16 in the source side and drain side access regions 82 and 83. The removal process can be carried out by means of dry-etch techniques, wet-etch techniques, or it can be carried out by a combination of dry-etch and wet-etch techniques. The removal process can be non-selective or selective. Thin Al_(x)Ga_(1-x)N layer(s) can be inserted as etch-stop layers between the III-N contact layer 17 and the III-N depleting layer 16. Chemical and thermal surface treatment can be carried out to recover the surface of the III-N depleting layer 16 after the removal of the III-N contact layer 17.

The III-N depleting layer 16 is removed in a portion of the source side and drain side access regions. The process of removing the III-N depleting layer 16 can be selected to substantially minimize damage to the surfaces of the exposed III-N materials in the source side and drain side access regions 82 and 83. The removal process can be carried out by means of dry-etch techniques, wet-etch techniques, or it can be carried out by a combination of dry-etch and wet-etch techniques. For example, a low-power dry-etch can be used to remove the bulk of the III-N contact layer 17 and the III-N depleting layer 16, followed by an acid wet-etch treatment to remove a remaining portion of the III-N depleting layer 16. The removal process can be non-selective or selective. Thin Al_(x)Ga_(1-x)N layer(s) can be inserted as etch-stop layers between the III-N depleting layer 16 and the III-N channel layer 15.

Alternatively, the process of removing the III-N depleting layer 16 can involve the partial removal of the III-N channel layer 15. The partial removal of the III-N channel layer 15 can be carried out by over-etching of the III-N depleting layer 16 in a continuous dry etching step, or carried out by a combination of multiple dry and wet etching steps. The etch rate of the III-N depleting layer 16 can be less than the etch rate of the III-N channel layer 15, and the process of removing the III-N depleting layer 16 can result in a substantial removal of the III-N channel layer in a portion of the source-side and drain-side access regions due to poor over-etch control. For example, before the etching process, the III-N channel layer 15 can have a thickness of 50 nm, and in the regions where the III-N depleting layer 16 has been removed, the over-etch of the III-N channel layer 15 can be 10-30 nm. In the regions where the III-N depleting layer has been removed, the thickness of the remaining III-N channel layer 15 can be greater than 20 nm. More than 50% of the thickness of III-N channel layer can be removed during the over-etch process of the III-N depleting layer 16.

Alternatively, the III-N depleting layer 16 and the III-N contact layer 17 can be selectively regrown by means of selective area regrowth. Selective area regrowth can bypass the need for removal processes.

A gate contact 23 (i.e., gate electrode) is formed over the III-N contact layer 17 in the gate region 81. The gate contact 23 can be formed of suitable conducting materials such as metal stacks (Al, Ti/Al, Ti/Al/Ni/Au, Ni/Au or the like) to achieve an ohmic contact with the III-N contact layer 17 and can be deposited by metal evaporation or sputtering or chemical vapor deposition or various atomic layer depositions (ALD). A post-gate deposition annealing process may optionally be performed after deposition of the gate contact 23. The post-gate deposition anneal may be performed in a gas ambient including oxygen or a forming gas (H₂+N₂). The post gate deposition anneal temperature can be greater than 300° C., or greater than 400° C. Finally, the gate contact 23 can be used as an etch mask to etch the III-N contact layer 17, such that the III-N contact layer 17 remains directly beneath the gate contact 23 but is etched away.

The detailed III-N material structure of region 30, which is indicated by the dashed region in FIG. 2 , is described in further detail in FIGS. 3A and 3B. This region highlights the different methods and material structures which can be used to implement the electrical connection of the gate contact 23 to the III-N depleting layer 16. A first method of forming an electrical connection of the gate contact 23 to the III-N depleting layer 16 can be implemented with a tunnel junction contact between the III-N depleting layer 16 and the III-N contact layer 17 and an ohmic contact between the III-N layer 17 and the gate contact 23, as shown in FIG. 3A. The tunnel junction contact can be formed by introducing a highly doped p-type GaN region 31 (i.e. p++ GaN) at the top surface of the III-N depleting layer 16 (e.g., between 2 nm and 1 μm thick with a doping density greater than 5×10¹⁹ cm⁻³) and a highly doped n-type GaN region 33 (i.e. n++ GaN) at the bottom surface of the III-N contact layer 17 (e.g., between 2 nm and 50 nm thick with a doping density greater than 5×10¹⁹ cm⁻³). The doping density of the highly doped regions should be such that the depletion width at the junction formed between the III-N contact layer 17 and the III-N depleting layer 16 is not more than a few nanometers (e.g. less than 10 nm), thus comparable to electron tunneling distance. Here, electrons can tunnel from the conduction-band of the III-N contact layer 174 and recombine with holes in the valence-band of the III-N depleting layer 16, creating an electrical connection between the gate contact 23 and the III-N depleting layer 16.

As shown in FIG. 3A, the quality of the tunnel junction in N-polar III-N materials can further be improved, e.g., by inserting a thin Al_(y)Ga_(1-y)N (0≤y≤1) layer 32 between the III-N depleting layer 16 and the III-N contact layer 17 (such that the interface region is p++ GaN/Al_(y)Ga_(1-y)N/n++ GaN). In N-polar III-N materials, the polarization charge of the inserted thin Al_(y)Ga_(1-y)N layer 32 further increases the accumulation of holes at the interface with the III-N depleting layer 16 and of electrons at the interface with the III-N contact layer 17, facilitating the tunneling and recombination processes. The thickness of the thin Al_(y)Ga_(1-y)N layer 32 can be between 0.5 nm to 5 nm, preferably between 0.5 nm and 2 nm, to facilitate tunneling. The thin Al_(y)Ga_(1-y)N layer 32 can also act to suppress the diffusion of the Mg (p-type dopant) in the III-N depleting layer 16 to the III-N contact layer 17, resulting in sharper doping profile and improved junction between the III-N depleting layer 16 and the III-N contact layer 17. Preferably, the thin Al_(y)Ga_(1-y)N layer 32 has high aluminum composition to (i) improve the Mg diffusion barrier, and (ii) increase the polarization charge and the accumulation of carriers at the tunnel junction resulting in better tunnel-junction contact resistance. The aluminum composition (y) can be greater than 50% (i.e., y>0.5), e.g., greater than 75%, e.g., greater than 90%, e.g., greater than 95%. The aluminum composition can be near 100% (i.e., y=1) such that the layer is AlN (e.g., unintentionally doped with Ga). In addition, a thin layer of In_(z)Ga_(1-z)N (0<z≤1) can be inserted between the Al_(y)Ga_(1-y)N layer and the n++ layer at the bottom of the III-N contact layer 17 which can be used to further improve electron accumulation at the tunnel junction interface. The indium composition in the In_(z)Ga_(1-z)N (0<z≤1) layer can be greater than 5% (i.e., z>0.05). The source contact metal stacks can be Al, Ti/Al, Ti/Al/Ni/Au, or the like.

Another method of forming an electrical connection of the gate contact 23 to the III-N depleting layer 16 can be implemented by omitting the deposition of the III-N contact layer 17 to allow the gate contact 23 to be in direct contact with the III-N depleting layer 16 (as shown in FIG. 3B). Wet-etch and surface cleaning techniques can be used to ensure that the surface of the III-N depleting layer 16 is smooth and free from damage. A high temperature anneal can be performed to improve the morphology and the composition of surface. High temperature annealing can be carried out in nitrogen/oxygen (N₂/O₂), nitrogen/ammonia (N₂/NH₃), forming gas (N₂/H₂). Temperature can range between 300C to 1000C, preferably between 700C to 900C. A gate metal stack can be deposited to make physical ohmic contact to the III-N depleting layer 16. The gate metal stack can be a high work function metal to ensure ohmic contact to the III-N depleting layer 16 (e.g., Al, Ti/Al, Pd, Pt, Ni/Au or the like). The contact between the gate metal and the III-N depleting layer 16 can be improved by introducing a thin highly doped p-type layer (e.g., between 2 nm and 50 nm thick with a doping density greater than 5×10¹⁹ cm⁻³) at the top of the III-N depleting layer 16.

Source and drain contacts 21 and 22 (i.e., source and drain electrodes), respectively, are on opposite sides of the gate contact 23. The source 21 and the drain 22 form an ohmic contact with the device 2DEG channel 19 that is formed in layer 15. The source contact 21 and the drain contact 22 can be formed by metal stacks (Al, Ti/Al, Ti/Al/Ni/Au, Ni/Au or the like) and/or n-type semiconductor regrowth. The source and drain contacts the channel layer 15. A recess can be at least partially formed in the III-N channel layer 15 to allow for improved contact of the source and drain electrodes to the 2DEG channel 19. A portion of the channel layer 15 below the source and drain contacts can be doped n-type, or an additional n-type layer can be inserted between the source and drain contacts and the channel layer 15 to improve the electrical contact of the source and drain metal to the 2DEG. The n-type semiconductor layer below the source and drain contacts can be selectively regrown. The regrown n-type semiconductor can have a doping larger than 1×10¹⁷ cm⁻³, preferably larger than 1×10¹⁹ cm⁻³. The metal stacks can be Al, Ti/Al, Ti/Al/Ni/Au, or the like. The contacts can be formed by metal evaporation and post-deposition annealing processes. Other ohmic contact processes can also be used including sputtering and dry etch processing.

An insulator layer 18 (e.g., a SiN layer) can be grown or deposited, at least in the source side access region 82 and the drain side access region 83, conformally over a top surface of the III-N contact layer 17 and the III-N depleting layer 16. The insulator 18 can, for example, be formed of or include aluminum oxide (Al₂O₃), silicon dioxide (SiO₂), silicon nitride (Si_(x)N_(y)), Al_(1-x)Si_(x)N, Al_(1-x)Si_(x)O, Al_(1-x)Si_(x)ON or any other wide bandgap insulator. The insulator 16 can be deposited either ex-situ, (e.g., with a different tool than that used for the growth of underlying III-N material), or in-situ, (i.e., with the same tool and during the same growth session used to growth the underlying III-N material). In case of in-situ deposition, the device surface is not exposed to air, thus not exposed to oxidizing elements (e.g., oxygen) and undesired impurities/contaminates. For this reason, in-situ deposition can result in superior interface qualities compared to ex-situ deposition (e.g., lower interface-states, lower fixed charge and/or lower trapped charge) resulting in superior electrical performance and better electric-field profile. In case of ex-situ deposition, the III-N material structure surface can be treated with chemical and thermal processes to improve surface quality (e.g., lower interface-states, lower fixed charge and/or lower trapped charge) prior to the deposition of the insulator layer 18. The insulator layer 18 can serve the function of passivation, neutralizing active traps states or fixed charge, and/or preventing charge-trapping and/or current leakage at surface states, and/or increasing the lateral breakdown between gate and drain contacts.

A method of forming the device 200 of FIG. 2 is as follows. A N-polar III-N material structure is formed. Forming the N-polar III-N material structure includes forming a III-N buffer layer 11 on a suitable substrate 10, for example on a miscut sapphire substrate. The III-N buffer layer 11 can consist of forming a thin N-polar GaN nucleation layer on the substrate and a carbon-doped GaN buffer layer on the nucleation layer. Next, a III-N back-barrier layer 14 is formed over the buffer layer. A III-N channel layer 15 is formed over the III-N back barrier layer 14, and a 2 dimensional electron gas (i.e. 2DEG layer) 19 is induced at the interface between layer 14 and layer 15. Next, a p-type III-N depleting layer 16 is formed over the III-N channel layer 15 and a n-type III-N contact layer 17 is formed over of the III-N depleting layer 16. The interface between the III-N depleting layer 16 and the III-N contact layer 17 can be formed through a tunnel junction. Forming the tunnel junction can comprise forming a p++/AlN/n++ material layer structure, for example, a 20 nm thick p++ layer (e.g. doped with magnesium with a concentration of 2×10¹⁹ cm⁻³) at the top surface of the III-N depleting layer 16, forming a thin AlN or AlGaN inter-layer (for example 1.5 nm thick) over the p++ layer, and forming a n++ layer, for example, a 20 nm thick n++ layer (e.g. doped with silicon with a concentration of 2×10¹⁹ cm⁻³) at the bottom surface of the III-N contact layer 17. Next, forming the device 200 comprises removing the III-N contact layer 17 to define the gate region 81, and removing the III-N depleting layer 16 in a portion of the drain-side access region 83 and the source side access region 82 of the device, for example by dry-etching, exposing a surface of the III-N material structure. Next, forming the device comprises anneal the device at high temperature to electrically activate the p-type III-N depleting layer 16. Next, source 21 and drain 22 ohmic contacts are formed by depositing metal stack containing aluminum (Al), Ti/Al or the like. Agate metal stack 23 (e.g., Ti/Al) is formed in the gate region 81 of the device forming a transistor. Finally, an insulator layer 18 can be formed over the surface of III-N layers.

The device of FIG. 2 operates as follows: when the gate 23 is biased relative to the source 21 at a voltage that is greater than the threshold voltage of the device (e.g., 0V), there is 2DEG charge below the gate 23 in the gate region, and therefore a continuous 2DEG from the source 21 to the drain 22. When a positive voltage is applied to the drain 22, electrons flow from the source 21, through the continuous 2DEG channel 19, and into the drain 22. A conventional current flows from the drain to the source, and the device is considered to be ON.

When the gate 23 is biased relative to the source 21 at a voltage that is higher than the threshold voltage of the device, the III-N depleting layer remains at substantially the same potential as the gate contact 23. As the voltage on the gate-source voltage is progressively decreased to a negative voltage, a positive electric field is created from the portion of the 2DEG that is directly beneath the III-N depleting layer 16. Holes are progressively drawn out from the depleting layer 16 and the ionized negative charge in III-N depleting layer 16 progressively depletes out electrons from the 2DEG. When the gate 23 is biased relatively to the source 21 at a voltage that is lower than a certain value (e.g., −5V, −10V, −20V), the depleting layer 16 is fully ionized (fully depleted). When the gate 23 is biased relative to the source 21 at a voltage that is lower than the threshold voltage of the device, there is no 2DEG below the charge depleting layer 16 (including the region 81 below the gate), and therefore the 2DEG is discontinuous between the source 21 and the drain 22. As discussed above, the doping levels, Al composition, and layer thicknesses, are chosen to achieve the desired full p-type ionization voltage and the desired threshold voltage of the device. When the device is used in cascode configuration, the threshold voltage of the device can be designed such that it is lower, in absolute value, than the breakdown voltage of the low-voltage normally-off common source device. For example, the threshold voltage can be higher (i.e., closer to 0V) than −30V, higher than −20V, higher than −10V. When the gate voltage relative to the source is lower than the full ionization voltage for layer 16 and lower than the threshold voltage of the device, any subsequent increase in drain voltage causes charge imaging from regions in or near the drain 22 to the gate 23. Because the III-N depleting layer 16 is fully depleted, it no longer remains at the gate potential and can withstand a voltage gradient. There is therefore a smooth change of potential from the drain 22 to the gate 23. This results in a larger, more uniform field before breakdown occurs, and hence a larger breakdown voltage than conventional HEMTs without charge depleting layers.

In addition to improving electric-field management and increasing the breakdown voltage, N-polar III-N devices with junction-based channel depleting layer, such as device 200, can have additional advantages with respect to conventional III-N devices, such as device 100, fabricated with industry standard dielectric-based field-plates (e.g., field plate 26). For example, III-N device 200 with channel depleting layer 16 can have a more stable threshold voltage than III-N device 100 with dielectric-based field-plates. Device 200 is free from dielectric bulk and interface traps formed during the field plate process, and in device 200 the holes generated in the depleting layer 16 by impact ionization can be efficiently removed by the junction gate-terminal. Also, when device 200 is exposed to high dv/dt and/or di/dt transients when switched in a cascode configuration, the junction gate-terminal formed with a junction-based III-N channel depleting layer 16 can turn on (i.e., forward-bias), clamping the gate-voltage to a relatively low value (for example, lower than 4 V) therefore preventing the gate failure during high transients. Whereas in III-N device 100 with a dielectric-based field-plate, the gate-voltage can increase in an uncontrolled manner when exposed to high dv/dt and/or di/dt transients when switched in a cascode configuration, reaching relatively high values (e.g., larger than 15 V) causing the gate dielectric degradation, such as charge-trapping, leakage and early failure. Also, the III-N device 200 with channel depleting layer 16 can allow a substantial improvement in electro-static discharge (ESD) protection, which may not be easily designed with dielectric-based field-plates devices, such as device 100. In addition, III-N devices with junction-based channel depleting layer, such as device 200 can allow the design of lateral devices with very high breakdown voltages (for example, greater than 1.2 kV, greater than 1.7 kV, greater than 3.3 kV, greater than 6.6 kV). This can be very difficult to practically implement using lateral III-N devices with dielectric-based field-plates, because the field-plate structure to accommodate such high breakdown voltages will become very long with many field-plate steps.

The electric-field profile in device 200 may need to be further refined. One reason for refinement is the possible existence of electric field peaks at abrupt discontinuities in the device structure. For example, the electric field may need to be optimized at the drain side of the gate region 81. Also, the electric field may need to be optimized at the side of the depleting layer 16 in region 83 adjacent to the drain 22, where the electric field tends to be higher because of abrupt discontinuities in the device structure. Another reason for optimization is if the areal density of ionized negative charge in the p-type III-N depleting layer 16 is different (e.g., lower or higher) than the areal density of ionized positive charge in the channel layer 15 and back-barrier layer 14. Some solutions to improve the electric-field profile of device 200 are described below.

The electric-field profile of device 200 can be improved with the addition of field-plate structures. As seen in FIG. 4A, a cross-sectional view of device 400 is shown. Device 400 is an N-polar depletion mode III-N transistor similar to the device 200 of FIG. 2 , which depicts the additional feature of a gate connected field plate 26. The field plate 26 includes a metal portion which extends over the insulator layer 18 into the drain side access region 83 towards the drain contact 22. Field plate 26 can be a single field plate or alternatively, field plate 26 can include multiple stacked field plates (as show in FIG. 4A), each including metal portions of different length extending toward the drain electrode.

In addition, a drain connected field-plate 27 can be used to control the electric field in the drain-side access region 83. Field-plate 27 is connected to the drain contact with a first end extending over the insulator layer 18 towards the gate region 81. The length of the drain connected field-plate 27 can be selected such that the first end of the field-plate extends over a portion of the III-N depleting layer 16 (e.g., the length of field-plate 27 can be greater than the separation 25 between the III-N depleting layer 16 and the drain contact 22). Field plate 27 can be a single field plate (as shown in FIG. 4A) or alternatively, field plate 27 can include multiple filed plates, each including metal portions of different length extending toward the gate electrode. Any excess mobile charge present in the end of the III-N depleting layer 16 adjacent to the drain contact 22 can be depleted by the drain connected field plate 27. The incorporation of the gate field plate 26 and/or drain connected field plate 27 can further help to manage the electric field in the gate region 81 and the drain side access region 83 and improve not only the device breakdown characteristics, but also the short-circuit withstanding time (SCWT). A more uniform electric field can lead to more uniform power density across the drain-side access region 83, therefore improving the dissipation of the short-circuit energy and increasing the time needed to reach the critical temperature to failure.

FIG. 4B depicts a cross-sectional view of device 410 which is similar to device 200 of FIG. 2 . Device 410 includes a III-N depleting layer 16′ which is coupled to the drain contact 22 and III-N contact layer 17′ which is used to enhance the electrical connection between layer 16′ and the drain contact 22. The III-N depleting layer 16 is electrically isolated from layer 16′ through separation 25′. The separation from the second end of depleting layer 16 to a first end of depleting layer 16′ can be greater than 0.5 um. For example, separation 25′ between the second end of the III-N depleting layer 16 and the first end of depleting layer 16′ can be between 0.5 μm and 10 μm. Also shown in device 410, the second end of the III-N depleting layer 16 which extends towards the drain contact 22 can be terminated at angle α<90°. For example, angle α can be between 100 and 80°. The sloped feature can help to manage the electric field near the end of the III-N depleting layer 16 in the drain-side access region 83 and improve breakdown voltage.

Alternatively, the sloped profile at the second end of the III-N depleting layer 16 can be formed with a staircase profile, as seen in device 420 of FIG. 4C. Device 420 includes a III-N depleting layer formed of plurality of discrete p-type layers, for example, with layers 16 a, 16 b, and 16 c. Each layer can include an Al_(x)Ga_(1-x)N interlayer formed between layer 16 a and layer 16 b, and between layer 16 b and layer 16 c, where x is between 0.5 and 1, and the thickness of the Al_(x)Ga_(1-x)N layer is between 0.5 nm and 5 nm. The AlGaN interlayer can be used as an etch-stop layer in the fabrication of the staircase profile. The composition and thickness of layers 16 a, 16 b, and 16 c can be similar or they can be different. For example, the p-type dopant concentration can consecutively decrease from the first discrete layer 16 a proximal to the III-N channel layer to the final discrete layer distal the III-N channel layer towards the gate electrode. Alternatively, the first and final discrete layer can have a higher dopant concentration that a plurality of layers formed between the first discrete layer and the final discrete layer. The plurality of p-type layers can include a first end which is adjacent to the drain electrode, and the separation of the first end to the drain electrodes increases from discrete layer proximal to the III-N channel layer to the discrete layer distal the III-N channel layer towards the gate electrode. The staircase profile can be used to mimic a sloped feature in FIG. 4B, therefore reducing the electric field at the second end of the depleting layer 16.

FIG. 4D is a cross-sectional view of device 430, which is similar to device 200 of FIG. 2 except that in device 430, the III-N depleting layer 16 can extend continuously from the source contact 21 to the drain contact 22. Here, a rectifying contact is formed between layer 16 and the source and drain contacts. The rectifying contact can be a Schottky barrier, a p-n barrier or a p-i-n barrier. A rectifying contact prevents the short-circuit between the gate 23 and drain 22 and between the gate 23 and source 21. When the drain and source contacts are formed with a low work function metal (such as Ti or Al), a rectifying Schottky barrier can be formed between the p-type depleting layer 16 and the low work function metals used for the drain and source ohmic contacts. Alternatively, the drain and source contacts can be formed with n-type III-N regrowth layer 31 below the source and drain contacts. Here, a rectifying p-n barrier is formed between the p-type depleting layer 16 and the n-type ohmic regrowth layer 31. In addition, the source and drain contacts can be formed with a III-N regrowth process that includes a III-N stack with an unintentionally doped (UID) GaN layer 32 and a n-type layer 31 formed below the source and drain contacts 21/22 (as seen in FIG. 4D). In this embodiment, a rectifying p-i-n barrier is formed between the III-N depleting layer 16 and the drain/source contacts 21/22. As an advantage, the device in FIG. 4D has no selective removal process for the depleting layer 16, therefore the channel layer 15 has no exposed etched surfaces that can cause current leakage, charge trapping, and presence of parasitic fixed and/or trapped charge that can degrade the electric-field profile.

In another embodiment, in device 440 shown in FIG. 4E, the III-N depleting layer 16 can be formed through a magnesium implantation into a portion of the top of the III-N channel layer 15. The use of implantation to can eliminate the need for a separate III-N depleting layer formed above the channel layer 15. This can result in a more planar device without the need to selectively remove the depleting layer in the source and drain side access regions, however other manufacturing aspects could become more difficult, such as the need for crystal damage recovery and dopant activation with very high temperature and very high pressure treatment and the associated need for control of Mg diffusion caused by high temperature exposure.

In another embodiment, device 450 of FIG. 4F is shown. Device 450 is similar to device 200 of FIG. 2 , except that the III-N depleting layer 16 is not removed in a portion of the source-side access region 82 and a portion of the drain-side access region 83. Instead, the lattice structure of the III-N depleting layer 16 in a portion of the source-side access region 82 and a portion of the drain-side access region 83 is intentionally damaged through ion-implantation (indicated by the downward arrows in FIG. 4F). This ion-implantation damage will render the charge depleting layer 16 semi-insulating in the separation regions 25 and region 27, therefore avoiding any short-circuit between the gate and source terminals or between the gate and drain terminals.

FIG. 5A is a cross-sectional view of device 500 which includes similar features as device 200 of FIG. 2 . However, device 500 of FIG. 5A incorporates a buried III-N depleting layer 516 which is formed between the III-N buffer layer 11 and the III-N back barrier layer 14. The III-N depleting layer 516 is contacting and electrically connected to the metal of the gate contact 23 through connecting metal 523, and in a similar manner as the connection of layer 16 to the gate 23, as previously described with respect to FIG. 2 , and FIGS. 3A/3B. As shown in FIG. 5A, the region 26 in which the buried depleting layer 561 is connected to metal 523 can be formed in a region outside the source and drain access regions, such as to not affect the 2DEG channel 19. The buried III-N depleting layer 516 can further improve the uniformity of the electric field profile. In this case, the 2DEG channel charge can partially or fully deplete over the entire device length between the source and drain contacts, when the gate-source voltage is lower than a minimum value (e.g. −5V, −10V, −20V) or lower than the device threshold voltage.

Optionally, when forming the device 500 with the buried III-N depleting layer 516, the III-N depleting layer 16 can be omitted. However, if both the III-N depleting layer 16 and the buried III-N depleting layer 516 are present, the electron density in the 2DEG charge can be increased (for example to 1.3×10¹³ cm⁻², 1.5×10¹³ cm⁻², 2×10 ¹³ cm⁻²) to achieve even lower specific on-state resistance, than compared to device 200 of FIG. 2 . The thickness and doping of the III-N depleting layer 16 and the buried III-N depleting layer 516 are designed such that they become fully depleted when gate-source voltage is lower than the threshold voltage. The gate voltage relative to the source at which the buried III-N depleting layer 516 becomes fully depleted can be less negative or more negative than the gate voltage relatively to the source at which the III-N depleting layer 16 becomes fully depleted.

FIG. 5B is a plan view of device 510 which includes similar features as device 500 of FIG. 5A. FIG. 5B includes device cross-section AA′ shown in FIG. 5C and device cross-section BB′ shown in FIG. 5D. Device 510 includes multiple 2DEG channels (e.g., two or more channels), shown as 19, 19′ and 19″, and multiple buried III-N depleting layers, as shown as layers 516, 516′ and 516″. The buried III-N depleting layers can be interleaved between the 2DEG channels 19, 19′ and 19″. The buried III-N depleting layers can be connected to each other by forming a trench in part of the gate region 81. The trench is formed into the III-N material structure, where the trench extends through the buried III-N layers 516, 516′ and 516″. Forming the trench is followed by a p-type GaN regrowth step, which forms a p-type III-N plug 518 and 518′, which connects to the buried III-N depleting layers, as shown in FIG. 5D. A III-N contact layer 17, and gate contact 23 is formed over the p-type III-N plugs 518 and 518′ to connect the gate 523 to the buried III-N depleting layers 516, 516′ and 516″. As seen in cross-section BB′ of FIG. 5D, the gate contact 523 is discontinuous, where separation 583 is formed between the p-type III-N plug 518 and the p-type III-N plug 518′. The separation 583 between the III-N plugs can be designed to maximize the surface of contact between the III-N plug 518 and 518′ and the buried III-N depleting layers 516, 516′, and 516″ and/or to respect manufacturing limits and lithographic process resolution, for example, the separation 583 can be between 0.5 μm and 5 μm. Cross-section AA′ in FIG. 5C is in region of device 510 where gate contact 23 is discontinuous. Device 510 with multiple 2DEG channels allow for the reduction of the device on-resistance. In addition, a device with multiple 2DEG channels including standard 2DEG charge density (e.g., lower or equal than 1×10¹³ cm⁻²) coupled with multiple buried III-N depleting layers can be preferred over a single channel (such as device 500) with ultra-high 2DEG charge (e.g., greater than 2×10¹³ cm⁻²) in order to maintain high charge mobility (which may degrade when a device with a single 2DEG channel charge exceeds a certain value, e.g., higher than 2×10¹³ cm⁻²) and to maintain low vertical electric field (which would exceed a critical breakdown electric field when a single 2DEG channel charge exceeds a certain value, e.g., 2×10¹³ cm⁻²).

In another embodiment, a multi-channel device with charge depleting layers can be implemented as show in device 520, where a plan view of device 520 is shown in FIG. 5E. FIG. 5E includes device cross-section CC′ shown in FIG. 5F and device cross-section DD′ shown in FIG. 5G. Device 520 is similar to device 510 of FIGS. 5B-5C, but formed without the buried III-N depleting layer 516, 516′ and 516″. Instead the charge depleting layer is implemented by forming trenches into the gate region 81 and into the drain-side access region 83. The trench is formed into the III-N material structure, where the trench extends through the multiple 2DEG channels 19, 19′ and 19″. Forming the trench is followed by a p-type GaN regrowth step, which forms a p-type III-N depleting layer 520 and 520′, as shown in cross-section DD′ of FIG. 5G. The charge depleting layers 520 and 520′ can be formed with regrowth p-type GaN. The charge depleting layer can be contacted in the gate region 81, with gate contact 523 and an optional III-N contact layer, such as layer 17. As seen in FIG. 5E, the gate contact 523 is discontinuous where cross-section CC′ of FIG. 5F is formed. As shown in cross-section DD′ of FIG. 5G, a separation 585 is formed between the p-type III-N depleting layers 520 and 520′. The separation 585 determines the threshold voltage of the 2DEG channels 19, 19′ and 19″. When the device 520 is used in cascode configuration, the separation 585 can be designed such that the absolute value of the threshold voltage of the device 520 is lower than the breakdown voltage of the low-voltage normally-off common-source device. For example, the separation 585 can be designed such that the absolute value of the threshold voltage of the device 520 is lower than 30V, or lower than 20V, or lower than 10V Cross-section CC′ in FIG. 5F is in a region of device 520 where gate contact 523 is discontinuous. The width and length of the trenches which form the III-N depleting layers 520 and 520′ and the doping of the III-N depleting layers 520 and 520′ can be optimized to achieve the desired electric-field uniformity in the drain-side access region 83.

Although device 200-500 of FIGS. 2-5A depict depletion mode devices, the properties of an N-polar material structure also allow the fabrication of an enhancement mode device with a III-N depleting layer. FIG. 6 shows a cross-sectional view of an enhancement mode device 600 which is fabricated in an N-polar direction. Device 600 includes a substrate 610, a III-N buffer layer 611, a III-N back-barrier layer 614, and a III-N channel layer 615, which can be similar in properties to those described in reference to the substrate 10, the III-N buffer layer 11, the III-N back-barrier layer 14, and the III-N channel layer 15 in device 200 of FIG. 2 . The thickness and composition of each of the III-N back-barrier layer 614 and III-N channel layer 615 is selected such that a two-dimensional electron gas layer 619 (2DEG) is induced in the III-N channel layer 615.

Device 600 includes a gate contact 623 formed in a gate region 681, a drain contact 622, and a source contact 621 all formed on the same side of the device, which is a side opposite the substrate 610. As shown in FIG. 6 , the source contact 621 is formed between the gate contact 623 and the drain contact 622 such that the device contacts are arrange in a gate-source-drain (G-S-D) configuration. Drain-side access region 683 is formed between the source contact 621 and the drain contact 622. Source-side access region 682 is formed between the source contact 621 and the gate contact 623.

A III-N depleting layer 616 is formed over at least a portion of the III-N channel layer 615, and can have similar characteristics as the III-N depleting layer 16 of FIG. 2 . As shown in FIG. 6 , the III-N depleting layer 616 can include at least a first portion which is in the gate-region 681, a second portion which is in the source-side access region 682 and a third portion which is laterally extending into the drain-side access region 683 between a source contact 621 and the drain contact 622. The III-N depleting layer 616 includes a first end and a second end, the first end being adjacent to the gate contact 623 and the second end being adjacent to the drain contact 622. The III-N depleting layer 616 is electrically isolated from the drain contact 622 through separation 625. The separation from the second end of depleting layer 616 to the drain contact 622 can be between 0.5 μm and 10 μm. Alternatively, the III-N depleting layer 616 can be in contact with the drain contact 625 (i.e., no separation 625) with a rectifying barrier, such as those described in device 430 of FIG. 4D.

A III-N body layer 630 and a III-N capping layer 617 are formed between the source contact 621 and the III-N depleting layer 616. The III-N body layer 630 and the III-N capping layer 617 are at least formed directly below the source contact 622 and extend throughout the source-side access region 682 and partially into the gate region 681. Layer 630 and 617 are electrically isolated from the drain contact 622 through separation 628, where separation 628 is greater than separation 625. The separation 628 can influence the maximum rated blocking voltage of the device. For example, for a device with a maximum blocking voltage of 650V, the separation 628 can be between 5 μm and 15 μm. For a device with a maximum blocking voltage of 1200 V, the separation 628 can be between 10 μm and 25 μm. Such a feature can be scaled to even larger separations, with higher maximum blocking voltages.

The III-N body layer 630 can be a p-type doped III-N layer (e.g., p-GaN). The p-type doped III-N body layer 630 can be doped with an active acceptor concentration density greater than 1×10¹⁶ cm⁻³ and lower than 2×10²⁰ cm⁻³, for example greater than 1×10¹⁸/cm⁻³ such that it is not fully depleted when the drain is biased at or below the maximum rated voltage of the device. If the III-N body layer 630 is p-type GaN doped with Mg, the device can be treated with high temperature annealing to render Mg dopants electrically active, and have a p-type doping concentration lower than 2×10¹⁹ cm⁻³ to avoid excessive incorporation of impurities (such as carbon and hydrogen) and to reduce electron scattering. In addition, a 0.5-5 nm AlGaN or AlN interlayer (not shown) can be disposed between the III-N body layer 630 and the III-N depleting layer 616. This AlGaN or AlN interlayer can serve as selective etch stop-layer to improve the control and the accuracy of the etching process used to remove the III-N body layer 630 in the drain side access region and protect the III-N depleting layer 616 from being over etched. The III-N body layer 630 can have a thickness between 20 nm and 5 μm. The III-N body layer 630 can have a thickness greater than 50 nm. The III-N body layer 630 can have a thickness greater than 200 nm.

Additionally, while in some cases the entire layer 630 is doped p-type, in other cases only a portion of the layer is doped p-type. For example, the layer 630 can include a series of p-doped portions in the vertical direction, each separated by undoped portions. When the III-N body layer 630 is doped p-type, the body layer will deplete out the electrons in the vertical channel in the gate region 81, thus causing the threshold voltage of the device to be positive. A positive voltage (with respect to the source contact) must be applied to the gate contact in order to connect the source contact to the 2DEG channel, therefore achieving E-mode operation mode. In addition, when the p-type doped body layer is electrically connected to the source contact 621, the source potential (i.e., the ground plane) can be very close (e.g. less than 20 nm) to the vertical channel. As such, the body layer 630 functions as a buried source-connected field plate structure, thus shielding the gate region from high-voltage stress, mitigating short-channel effects such as drain induced barrier lowering (i.e. DIBL) and suppressing V_(TH) instabilities. The p-type body can collect holes generated in the high-voltage section of the III-N device preventing them from being trapped under the gate, reducing V_(TH) instabilities. The normally-off gate with p-type body can control the on-state saturation current (I_(D,SAT)) of the device, therefore can be used to control the short-circuit withstanding time (SCWT). The p-type body can also enable the design and integration of electrostatic discharge (ESD) protection structures, which can improve device reliability.

Alternatively, the p-type of the III-N body layer 630 can be achieved by polarization-induced doping (e.g., by grading the bandgap of the layer without introducing any dopant impurities). In this case, an aluminum or indium composition of the III-N body layer 630 is graded to induce a bulk negative polarization-charge which can attract holes, rendering the III-N body layer 630 p-type. A graded III-N body layer 630 has a composition that is graded (e.g., continuously graded), from the side adjacent the III-N channel layer 615 to the side opposite the III-N channel layer 615. The composition of a graded p-type III-N body layer 630 is selected such that the gradient of the polarization field is positive in the [000-1] direction. For example, the III-N body layer 630 in the III-N device 600 can be formed of Al_(y)Ga_(1-y)N (0≤y≤1), where the y in the side of the III-N body layer 630 adjacent the III-N channel layer is equal to the y of the III-N channel layer 615 and increases (e.g., continuously increases) from the side adjacent the III-N channel layer 615 to the side opposite the III-N channel layer 615. Alternatively, the III-N body layer 630 can be formed of In_(y)Ga_(1-y)N (0≤y≤1), where y decreases (e.g., continuously decreases) from the side adjacent the III-N channel layer 615 to the side opposite the III-N channel layer 615.

Alternatively, the III-N body layer 630 can be formed using a semi-insulating or insulating GaN layer (e.g., i-GaN). The i-GaN layer can be rendered semi-insulating, insulating or substantially free of n-type mobile carriers by including dislocations or point defects in the layer, or by doping the layer with compensating elements, such as Fe and/or C. The implementation of an i-GaN body layer instead of a p-type GaN body layer can simplify the fabrication process because there is no need to control the Mg doping profile and the Mg activation of a p-type GaN body layer or the grading profile. However, because of the insulating nature of the i-GaN body, an electrical connection to the source contact cannot be used to control the voltage potential of the body layer 617, and hence an i-GaN body may not provide the same benefits in terms of threshold voltage and field-plating when compared to the implementation of the p-type III-N body layer.

The III-N capping layer 617, for example a n-type GaN layer, is formed over the III-N body layer 630 between the gate 623 and the source 621. The III-N capping layer provides a current path in the source side access region 682 between the source contact 621 and the gate region 681. The thickness of the III-N capping layer can be between 10 nm and 1 μm. The III-N capping layer can have a thickness greater than 10 nm. The III-N capping layer 617 can be doped with donors (e.g., silicon). The doping concentration of the III-N capping layer can be high enough to yield an electron concentration density greater than 1×10¹⁶ cm⁻³. The thickness and net n-type doping of the III-N capping layer 617 can be sufficiently high such that layer 617 is not fully depleted of free electrons by the III-N body layer 630, for example, thickness can be greater than 50 nm and average n-type doping greater than 1×10¹⁸ cm⁻³. The n-type doping can be greater than 1×10¹⁹ cm⁻³.

The thickness and n-type doping of the III-N capping layer 617 can be sufficiently high to yield very low sheet-resistance. The sheet-resistance of the III-N capping layer 617 can be lower than 100-200Ω/□. The sheet-resistance of the III-N capping layer 617 can be lower than the sheet-resistance of the III-N channel layer 615. This represents an unusual advantage of this device architecture: the source side access region 682 is realized on a fully independent layer with respect to the drain side access region 683. Therefore, the III-N capping layer 617 in the source side access region 682 can be engineered to attain very small source access resistance.

The III-N capping layer 617 and III-N body layer 630 are removed in a portion of the gate region 681 to create a vertical (or semi-vertical or slanted) gate module. The removal of the III-N material structure in these regions can herein be referred to as a “trench recess”. The process of forming the trench recess can be optimized to minimize damage to the surfaces of the exposed III-N channel layer 615 in the gate region 681. The selective removal process can be carried out by means of dry-etch techniques, wet-etch techniques, or by a combination of dry-etch and wet-etch techniques. For example, a low-power dry-etch can be used to remove the bulk of the III-N capping layer 617 III-N body layer 630 in the gate region 681, followed by an acid wet-etch treatment to remove a remaining portion of the layer 630.

The process of removing the III-N body layer 630 can involve the partial removal of the III-N channel layer 615 in the gate region 681. The partial removal of the III-N channel layer 615 can be carried out by over-etching of the III-N body layer in a continuous dry etching step, or carried out by a combination of multiple dry and wet etching steps. The remaining thickness of the III-N channel layer 615 determines the capacitance between the channel (e.g., 2DEG) and the gate contact 623. Before the trench etch processing, the III-N channel layer 615 can be, for example, thicker than 150 nm. In the region where the III-N body layer 630 has been removed, the overtech of the III-N channel layer can be 20-100 nm. In the region where the III-N body layer 630 has been removed, the thickness of the III-N channel layer 615 remaining can be greater than 50 nm. More than 50% of the thickness of III-N channel layer can be removed during the overetch of the trench process.

A gate insulator layer 634 (e.g., a gate dielectric layer), is grown or deposited, at least in the gate region 681, conformally over the vertical sidewall of the III-N body layer 630. The gate insulator layer 634 can be over the top surface of the III-N capping layer 617 and have a first portion which extends towards the source 21. The gate insulator 34 can be over the top surface of the III-N channel layer 16 and have a second portion which is between the channel layer 615 and the gate contact 623. The gate insulator layer 634 can have similar or properties to insulating 18 of FIG. 2 , or they can be different.

The gate contact 623 (i.e., gate electrode) is formed conformally over the gate insulator layer 634 and the vertical sidewall portion of the III-N body layer 630 in the gate region 681. The gate contact 623 can be over the top surface of the III-N capping layer 617 and have a first portion which extends towards the source 621. Gate contact 623 can have similar material characteristics as gate contact 23 of FIG. 2 or gate contact 23 of FIG. 3B.

Insulating layer 618 is formed over the device between the gate, source, and drain contacts to passivate the top surface of the device. Insulating layer 618 can be similar to insulating layer 18 of FIG. 2 .

Source contact 621 is electrically connected to the III-N body layer 630. This connection can be implemented through direct contact, or tunnel junction. These methods of contact can be similar to those described in FIG. 3A and FIG. 3B, which were used to connect the gate contact 23 of device 200 to the III-N depleting layer 16.

Device 600 of FIG. 6 operates as follows: when the gate contact 623 is biased relative to the source 621 at a voltage that is greater than the threshold voltage of the device, an inversion channel forms at the vertical interface between the gate insulator layer 634 and the III-N body layer 630 in the gate region 681 of the device, thereby electrically connecting the source contact 621 to the 2DEG channel 619. When a positive voltage is applied to the drain 622, electrons flow from the source 621, through the source-side access region 682, through the inversion channel formed near the vertical interface between the gate insulator layer 634 and the III-N body layer 630 in the gate region 681, into the 2DEG channel 619, and to the drain 622 forming a continuous device channel between the source contact 621 and the drain contact 622. A conventional current flows from the drain 622 to the source 621, and the device is considered to be ON.

When the gate 623 is biased relative to the source 621 at a voltage that is lower than the threshold voltage of the device, the p-type dopants of the III-N body layer 630 fully deplete the charge between the vertical interface between of the gate insulator layer 634 and the III-N body layer 630 such that there is no inversion channel formed in the gate region 681 and therefore the device channel is discontinuous between the source contact 261 and the 2DEG channel 619. Furthermore, when a positive voltage is applied to the drain 622, the III-N channel layer 615 and the III-N depleting layer 616 will gradually deplete of mobile charge. When the drain voltage is higher than a minimum value (e.g., 5V, 10V, 20V), the III-N channel layer 615 and the III-N depleting layer 616 will become fully depleted (i.e., pinched-off) in the drain-side access region 683, therefore being able to withstand high voltage operation, similar to the device 200 of FIG. 2 . The lateral portion of the channel in the drain side access region 683, the charge-depleting layer 616 and the passivation insulating layer 618 can be constructed to withstand high voltages, for example greater than 200V, greater than 300V, greater than 600V, greater than 900V, greater than 1200V, greater than 3300V, or greater than 10 kV.

The III-N device 600 can be a transistor, a bidirectional switch or four quadrant switch (FQS), and/or any suitable semiconductor device. Traditional III-N devices with a lateral 2DEG gate region typically exhibit a shift in threshold voltage (Vth) after being stressed under continuous use, as previously described. However, in the device 600 of FIG. 6 , the use of the III-N body layer 630 can reduce the V_(TH) shift of the device closer to 0V, when compared to a traditional lateral III-N device without the a III-N body layer.

Furthermore, when the gate 623 is biased relative to the source 621 at a voltage that is lower than the threshold voltage of the device, and a sufficient reverse (i.e., positive) voltage bias is applied to the source contact relative to the drain contact, a body diode is formed between the III-N body layer 630 and the III-N channel layer 615, and current can flow through the body diode in the reverse direction from the source contact 621 to the drain contact 622. This is referred to as reverse conduction mode.

Another implementation of a III-N device 700 is shown in FIG. 7 . Device 700 is configured to operate as a bidirectional switch, sometimes also referred to as a four-quadrant switch (i.e., FQS). Similar to other devices described herein, device 700 includes a substrate 10 (although the substrate is optional), a III-N material structure including III-N layers 11 and 14 on the substrate 10, a 2DEG channel 19 in the III-N material structure, an insulator layer 18 on the III-Nitride material structure. Device 700 also includes a first source contact 21, a second source contact 721, a first gate electrode 23 formed on a first p-type III-N depleting layer 16, and a second gate electrode 723 formed on a second p-type III-N depleting layer 716. The first source contact 21 and the second source contact 721 each electrically contact the 2DEG channel 19. As in previous implementations, device 700 can also include gate-connected and/or source-connected field plates (not shown) to help electric-field management further. The first III-N depleting layer 16 can be designed such that when gate bias is applied to the first gate electrode 23 relative to the first source contact 21 below the threshold voltage of the device, and the second source contact 721 is biased at a higher voltage than the first source contact 124, the device channel in the gate region corresponding to gate 23 is depleted of charge, and the bidirectional switch is in the OFF state, but the device channel in the gate region corresponding to gate 23 becomes readily conductive when 0V is applied to the first gate electrode 23 relative to the first source contact 21 while the second source contact 721 is still biased at a higher voltage than the first source contact 21. The III-N depleting layer 716 can be designed such that when gate bias applied to the second gate electrode 723 relative to the second source contact 721 and the second source contact 721 is biased at a lower voltage than the first source contact 21, the device channel in the gate region corresponding to gate 723 is depleted of charge, and the bidirectional switch is in the OFF state, but the device channel in the gate region corresponding to gate 723 becomes readily conductive when a 0V is applied to the second gate electrode 38 relative to the second source contact 721 while the second source contact 721 is still biased at a lower voltage than the first source contact 21. When gate 23 is biased OFF (i.e., below its threshold voltage relative to contact 21) and gate 723 is biased OFF (i.e., below its threshold voltage relative to contact 721), the device 700 blocks voltage between contacts 21 and 721 of either polarity (i.e., both when the voltage of contact 21 is greater than that of contact 721 and when the voltage of contact 721 is greater than that of contact 21). When gate 35 is biased ON (i.e., above its threshold voltage relative to contact 21) and gate 738 is biased ON (i.e., above its threshold voltage relative to contact 721), the device 700 can conduct current in either direction.

A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the techniques and devices described herein. 

What is claimed is:
 1. A III-N device, comprising: a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N depleting layer, wherein the III-N channel layer includes a 2DEG channel formed therein; a source electrode and a drain electrode, each of which being electrically connected to the 2DEG channel; a gate electrode between the source and the drain, the gate being over the III-N layer structure; wherein the p-type III-N depleting layer includes a first portion that is between the gate electrode and the drain electrode; and the p-type III-N depleting layer is electrically connected to the gate electrode and electrically isolated from the source and drain electrodes.
 2. The device of claim 1, wherein the III-N material structure is grown in an N-polar orientation.
 3. The device of claim 1, wherein a dopant concentration in the p-type III-N depleting layer is such that an areal p-type doping density in the p-type III-N layer is in the range of 10-150% of an areal sheet charge density of mobile charge in the 2DEG channel.
 4. The device of claim 1, further comprising a first Al_(x)Ga_(1-x)N layer between the p-type III-N depleting layer and the III-N channel layer, wherein x is between 0.5 and 1, and the thickness of the Al_(x)Ga_(1-x)N layer is between 0.5 nm and 5 nm.
 5. The device of claim 4, further comprising an n-type GaN layer between the gate electrode and the p-type III-N depleting layer.
 6. The device of claim 5, further comprising a second Al_(x)Ga_(1-x)N layer between the n-type GaN layer and the p-type III-N depleting layer, wherein x is between 0.5 and 1, and the thickness of the Al_(x)Ga_(1-x)N layer is between 0.5 nm and 5 nm.
 7. The device of claim 6, further comprises a second n-type GaN layer between the first n-type GaN layer and the second Al_(y)Ga_(1-y)N layer, and a second p-type GaN layer between the p-type III-N depleting layer and the second Al_(y)Ga_(1-y)N layer, wherein the second n-type GaN layer and the second p-type GaN layer have a doping density greater than the n-type GaN layer and the p-type III-N depleting layer.
 8. The device of claim 1, wherein the p-type III-N depleting layer includes a first end adjacent the drain electrode and a separation from the first end to the drain electrode is between 0.5 μm and 5 μm.
 9. The device of claim 8, wherein the gate electrode includes a field plate, and the field plate at least partially extends over the first portion of the p-type III-N depleting layer.
 10. The device of claim 7, wherein the drain electrode includes a field plate, and a portion of the field plate at least partially extends over the first portion of the p-type III-N depleting layer.
 11. The device of claim 8, wherein a sidewall angle of the first end relative to a bottom surface of the p-type III-N depleting layer is between 10-80 degrees.
 12. The device of claim 1, wherein the p-type III-N depleting layer includes a plurality of p-type layers over the III-N channel layer where each layer is separated by an Al_(x)Ga_(1-x)N layer, wherein x is between 0.5 and 1, and the thickness of the Al_(x)Ga_(1-x)N layer is between 0.5 nm and 5 nm.
 13. The device of claim 12, where each plurality of p-type layers includes a first end adjacent to the drain electrode, and the separation of the first end to the drain electrode increases from the p-type layer proximal the III-N channel layer to the p-type layer distal the III-N channel layer.
 14. A transistor, comprising: an N-polar III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N layer; a source electrode and a drain electrode; a gate electrode between the source and the drain, the gate being over the III-N layer structure and the p-type III-N layer is electrically connected to the gate electrode; and a 2DEG channel in the III-N channel layer, wherein the N-polar III-N layer structure is configure such that the 2DEG channel extends continuously from the source electrode to the drain electrode when the gate is biased at 0V with respect to the source.
 15. The transistor of claim 14, wherein the p-type III-N layer includes at least a first portion between the gate electrode and the drain electrode.
 16. A transistor, comprising: a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N depleting layer, wherein the III-N channel layer includes a 2DEG channel formed therein; a source electrode and a drain electrode, each of which being electrically connected to the 2DEG channel; a gate electrode between the source and the drain, the gate being over the III-N layer structure; wherein a first portion of the p-type III-N depleting layer is electrically connected to the gate electrode; and a second portion of the p-type III-N depleting layer is electrically connected to the drain electrode; and the first portion and the second portion are electrically isolated from each other.
 17. The transistor of claim 16, wherein a separation between the first portion of the III-N depleting layer and the second portion of the III-N depleting layer is between 0.5 μm and 5 μm.
 18. The transistor of claim 17, further comprising a first n-type GaN layer between the gate electrode and the first portion of the p-type III-N depleting layer, and a second n-type GaN layer between the drain electrode and the second portion of the III-N depleting layer.
 19. The transistor of claim 18, wherein the gate electrode is electrically connected to the first portion of the p-type III-N depleting layer with a tunnel junction and the drain electrode is electrically connected to the second portion of the III-N depleting layer with a tunnel junction.
 20. A III-N device comprising: a III-N layer structure comprising a III-N channel layer and a 2DEG channel therein, a III-N barrier layer under the III-N channel layer, and a p-type III-N layer over the III-N channel layer; a source electrode and a drain electrode; and a gate electrode between the source electrode and the drain electrode, the gate being over the III-N layer structure and electrically connected to the p-type III-N layer; wherein the p-type III-N layer includes a first portion that is between the gate and the drain electrodes; wherein the III-N device has a negative threshold voltage; and wherein the III-N device is configured such that; when the gate is biased relative to the source electrode at a negative voltage above a first minimum voltage, the 2DEG channel extends continuously from the source electrode to the drain electrode; and when the gate is biased relative to the source electrode at a voltage below the first minimum voltage and above the threshold voltage, the p-type III-N layer is depleted of holes in the device region between the gate and drain electrodes.
 21. The device of claim 20, wherein the first minimum voltage is below −5V.
 22. The device of claim 20, wherein the device is configured such that, when the gate is biased above the first minimum voltage and the drain electrode is biased above a second minimum voltage, the p-type III-N layer is depleted of holes in the device region between the gate and drain electrode.
 23. The device of claim 22, wherein the second minimum voltage is above 5V. 